A fully-buffered dual in-line memory module (FB-DIMM) may utilize an advanced memory buffer (AMB), which is typically disposed on one side of the module. An AMB may have three ports of communication. These ports include high speed serial lanes, which communicate to and from a host mother board chipset via an edge connector and possibly other FB-DIMMs, and an SMBus that provides slow speed two wire serial access for writing and reading configuration and status registers. A high speed parallel interface is also provided that supports bidirectional communication with all DRAMs on the DIMM. This FB-DIMM architecture represents the next generation of DIMMs that can increase the density and bandwidth of a single DIMM and support greater mother board expansion to include more DIMMs.
During normal modes of operation, an FB-DIMM provides no direct access from the edge connector to the DRAMs on the module. Instead, the AMB is responsible for communicating with the edge connector and generating and receiving all signals to and from the DRAMs. The AMB is also responsible for generating the correct timing of signals to and from the DRAMs. Typical AMBs are designed as generic devices that may operate at a data rate from 3.2 Gb/s to 4.8 Gb/s and support as few as nine and as many as 36 DRAMs of different type, while also supporting x4 and x8 data width modes. In order to support this wide range in operating conditions, an AMB includes internal registers that are programmable with configuration data. These internal registers may be accessible by either the SMBus or in-band commands on the high speed serial lanes.
As will be understood by those skilled in the art, an AMB may experience reduced timing margins when the FB-DIMM is running at its maximum speed (e.g., the 4.8 Gb/s rate translates to a 400 MHz DRAM clock or an 800 Mb/s DDR data interface). At this maximum speed, the clock period is nominally 2.5 ns, and the half period or data eye maximum is 1.25 ns. Generating signals that meet these reduced timing margins is difficult because of the presence of timing skew between data, address, command, strobe and clock signals generated to and from the DRAMs. This timing skew is at least partially caused by the physical line length differences between the AMB and the closest and farthest DRAMs on both sides of the DIMM. Accordingly, notwithstanding the advantages of using FB-DIMMs having AMBs to communicate with mother board chipsets, there continues to be a need for more advanced AMBs having better timing skew control.